1. Field of the Invention
The present invention relates to logic circuits comprising field effect transistors (FET's) and more particularly to such a circuit for driving a word or bit line in a monolithic memory.
2. Description of the Prior Art
The cross-referenced patent describes an FET driver circuit of the same type as the present invention. When a driver circuit of this type is used to drive one of a plurality of word or bit lines to select a particular memory cell, certain problems might arise resulting in false selection of bit or word line and degraded performance. These problems arise due to various timing considerations described later herein and also because of capacitive coupling from other bit lines into the output node of the present driver circuit. In the cross reference patent, the output node is charged or discharged through the drain to source path of the driving FET when the gating electrode renders said driving FET conductive. However, when the gating electrode is not activated, it is possible for a trapped charge to develop on the output node. The problem of trapped charge on the output node could be partially eliminated by simply placing a discharge path from the output node to ground. However, such discharge paths known in the prior art have structural connections and timing restrictions on their mode of operation which makes them inoperative to solve the problems addressed by the present invention.